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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">DVPRCTX, Data Value Prediction Restriction by Context</h1><p>The DVPRCTX characteristics are:</p><h2>Purpose</h2>
        <p>Data Value Prediction Restriction by Context applies to all Data Value Prediction Resources that predict execution based on information gathered within the target execution context or contexts.</p>

      
        <div class="note"><span class="note-header">Note</span><p>The prediction of the PSTATE.{N,Z,C,V} values is not considered a data value for this purpose.</p></div>
      
        <p>Data value predictions determined by the actions of code in the target execution context or contexts appearing in program order before the instruction cannot exploitatively control speculative execution occurring after the instruction is complete and synchronized.</p>

      
        <p>This instruction is guaranteed to be complete following a DSB that covers both read and write behavior on the same PE as executed the original restriction instruction, and a subsequent context synchronization event is required to ensure that the effect of the completion of the instructions is synchronized to the current execution.</p>

      
        <div class="note"><span class="note-header">Note</span><p>This instruction does not require the invalidation of prediction structures so long as the behavior described for completion of this instruction is met by the implementation.</p><p>On some implementations the instruction is likely to take a significant number of cycles to execute. This instruction is expected to be used very rarely, such as on the roll-over of an ASID or VMID, but should not be used on every context switch.</p></div>
      <h2>Configuration</h2><p>This instruction is present only when AArch32 is supported and FEAT_SPECRES is implemented. Otherwise, direct accesses to DVPRCTX are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>DVPRCTX is a 32-bit System instruction.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-27_27">GVMID</a></td><td class="lr" colspan="1"><a href="#fieldset_0-26_26">NS</a></td><td class="lr" colspan="2"><a href="#fieldset_0-25_24">EL</a></td><td class="lr" colspan="8"><a href="#fieldset_0-23_16">VMID</a></td><td class="lr" colspan="7"><a href="#fieldset_0-15_9">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">GASID</a></td><td class="lr" colspan="8"><a href="#fieldset_0-7_0">ASID</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">Bits [31:28]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-27_27">GVMID, bit [27]</h4><div class="field">
      <p>Execution of this instruction applies to all VMIDs or a specified VMID.</p>
    <table class="valuetable"><tr><th>GVMID</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Applies to specified VMID for an EL0 or EL1 target execution context.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Applies to all VMIDs for an EL0 or EL1 target execution context.</p>
        </td></tr></table><p>For target execution contexts other than EL0 or EL1, this field is <span class="arm-defined-word">RES0</span>.</p>
<p>If the instruction is executed at EL0 or EL1, this field has an Effective value of 0.</p>
<p>If EL2 is not implemented or not enabled for the target Security state, this field is <span class="arm-defined-word">RES0</span>.</p></div><h4 id="fieldset_0-26_26">NS, bit [26]</h4><div class="field">
      <p>Security State.</p>
    <table class="valuetable"><tr><th>NS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Secure state.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Non-secure state.</p>
        </td></tr></table>
      <p>If the instruction is executed in Non-secure state, this field has an Effective value of 1.</p>
    </div><h4 id="fieldset_0-25_24">EL, bits [25:24]</h4><div class="field">
      <p>Exception Level. Indicates the Exception level of the target execution context.</p>
    <table class="valuetable"><tr><th>EL</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>EL0.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>EL1.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>EL2.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>EL3.</p>
        </td></tr></table>
      <p>If the instruction is executed at an Exception level lower than the specified level, or is specified to apply to a combination of Exception level and Security state that is not implemented, this instruction is treated as a NOP.</p>
    </div><h4 id="fieldset_0-23_16">VMID, bits [23:16]</h4><div class="field"><p>Only applies when bit[27] is 0 and the target execution context is either:</p>
<ul>
<li>EL1.
</li><li>EL0 when (<a href="AArch64-hcr_el2.html">HCR_EL2</a>.E2H==0 or <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE==0) or EL2 is using AArch32 state.
</li></ul>
<p>Otherwise this field is <span class="arm-defined-word">RES0</span>.</p>
<p>When the instruction is executed at EL1, this field is treated as the current VMID.</p>
<p>When the instruction is executed at EL0 and (<a href="AArch64-hcr_el2.html">HCR_EL2</a>.E2H==0 or <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE==0 or ELUsingAArch32(EL2)), this field is treated as the current VMID.</p>
<p>When the instruction is executed at EL0 and (<a href="AArch64-hcr_el2.html">HCR_EL2</a>.E2H==1 and <a href="AArch64-hcr_el2.html">HCR_EL2</a>.TGE==1 and !ELUsingAArch32(EL2)), this field is ignored.</p>
<p>If EL2 is not implemented or not enabled for the target Security state, this field is <span class="arm-defined-word">RES0</span>.</p></div><h4 id="fieldset_0-15_9">Bits [15:9]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-8_8">GASID, bit [8]</h4><div class="field">
      <p>Execution of this instruction applies to all ASIDs or a specified ASID.</p>
    <table class="valuetable"><tr><th>GASID</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Applies to specified ASID for an EL0 target execution context.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Applies to all ASIDs for an EL0 target execution context.</p>
        </td></tr></table><p>For target execution contexts other than EL0, this field is <span class="arm-defined-word">RES0</span>.</p>
<p>If the instruction is executed at EL0, this field has an Effective value of 0.</p></div><h4 id="fieldset_0-7_0">ASID, bits [7:0]</h4><div class="field"><p>Only applies for an EL0 target execution context and when bit[8] is 0.</p>
<p>Otherwise, this field is <span class="arm-defined-word">RES0</span>.</p>
<p>When the instruction is executed at EL0, this field is treated as the current ASID.</p></div><div class="access_mechanisms"><h2>Executing DVPRCTX</h2><p>Accesses to this instruction use the following encodings in the System instruction encoding space:</p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0111</td><td>0b0011</td><td>0b101</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    if !ELUsingAArch32(EL1) &amp;&amp; !(EL2Enabled() &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11') &amp;&amp; SCTLR_EL1.EnRCTX == '0' then
        if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.AArch32SystemAccessTrap(EL2, 0x03);
        else
            AArch64.AArch32SystemAccessTrap(EL1, 0x03);
    elsif ELUsingAArch32(EL1) &amp;&amp; SCTLR.EnRCTX == '0' then
        if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TGE == '1' then
            AArch64.AArch32SystemAccessTrap(EL2, 0x03);
        elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TGE == '1' then
            AArch32.TakeHypTrapException(0x00);
        else
            UNDEFINED;
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; != '11' &amp;&amp; HSTR_EL2.T7 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T7 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL1) &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; != '11' &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HFGITR_EL2.DVPRCTX == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.&lt;E2H,TGE&gt; == '11' &amp;&amp; SCTLR_EL2.EnRCTX == '0' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    else
        AArch32.RestrictPrediction(R[t], RestrictType_DataValue);
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T7 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T7 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x03);
    else
        AArch32.RestrictPrediction(R[t], RestrictType_DataValue);
elsif PSTATE.EL == EL2 then
    AArch32.RestrictPrediction(R[t], RestrictType_DataValue);
elsif PSTATE.EL == EL3 then
    AArch32.RestrictPrediction(R[t], RestrictType_DataValue);
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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